[1] |
Collaert N. Device architectures for the 5 nm technology node and beyond[M]. Taibei: Semicon, 2016.
|
[2] |
Moroz V. Technology inflection points: Planar to FinFET to nanowire[C]// International Symposium on Physical Design (ISPD). Santa Rosa:2016.
|
[3] |
Horiguchi N. Entering the nanosheet transistor era, eetimes report[EB/OL]. [2021-08-12]. https://www.EEtimes.com/entering-the-nanosheet-transistor-era/.
|
[4] |
Bernard E, Ernst T, Guillaumot B, et al. Novel integration process and performances analysis of low standby power (LSTP) 3D multi-channel CMOSFET (MCFET) on SOI with metal / high-κ gate stack[C]// Symposium on VLSI Technology. Piscataway: IEEE Press, 2008, doi: 10.1109/VLSIT.2008.4588546.
DOI
|
[5] |
Barraud S, Lapras V, Previtali B, et al. Performance and design considerations for gate-all-around stacked-nano-wires FETs[C]// IEEE International Electron Devices Meeting (IEDM). Piscataway: IEEE Press, 2018, doi: 10.1109/IEDM.2017.8268473.
DOI
|
[6] |
Choi Y H, Lee K, Kim K Y, et al. Simulation of the effect of parasitic channel height on characteristics of stacked gate-all-around nanosheet FET[J]. Solid-State Electronics, 2020, 164: doi: 10.1016/j.sse.2019.107686.
DOI
|
[7] |
Loubet N, Hook T, Montanini P, et al. Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET[C]// IEEE Symposium on VLSI Technology. Piscataway: IEEE Press, 2017, doi: 10.23919/VLSIT.2017.7998183.
DOI
|
[8] |
Zhang J, Frougier J, Greene A, et al. Full bottom dielectric isolation to enable stacked nanosheet transistor for low power and high performance applications[C]// IEEE International Electron Devices Meeting (IEDM). Piscataway: IIEEE Press, 2020, doi: 10.1109/IEDM19573.2019.8993490.
DOI
|
[9] |
Jeong J, Yoon J S, Lee S, et al. Comprehensive analysis of source and drain recess depth variations on silicon nanosheet FETs for sub 5-nm node SoC application[J]. IEEE Access, 2020, 8: 35873-35881.
DOI
URL
|
[10] |
Chen K, Yang J, Liu T, et al. Source/Drain trimming process to improve gate-all-around nanosheet transistors switching performance and enable more stacks of nanosheets[J]. Micromachines, 2022, 13(7), doi: 10.3390/mi13071080.
DOI
|
[11] |
Packan P, Cea S, Deshpande H, et al. High performance Hi-K + metal gate strain enhanced transistors on (110) silicon[C]// IEEE International Electron Devices Meeting (IEDM). Piscataway: IEEE Press, 2009, doi: 10.1109/IEDM.2008.4796614.
DOI
|
[12] |
Nainani A, Gupta S, Moroz V, et al. Is strain engineering scalable in FinFET era: Teaching the old dog some new tricks[C]// IEEE International Electron Devices Meeting (IEDM). Piscataway: IEEE Press, 2013, doi: 10.1109/IEDM.2012.6479065.
DOI
|
[13] |
Thompson S E, Armstrong M, Auth C, et al. A 90-nm logic technology featuring strained-silicon[J]. IEEE Transactions on Electron Devices, 2004, 51(11): 1790-1797.
DOI
URL
|
[14] |
Loubet N. Enablement of next generation high performance nanosheet transistors[C]// IEEE International Electron Devices Meeting (IEDM). San Francisco:2020.
|
[15] |
Schmidt D, Durfee C, Li J, et al. In-line raman spectro- scopy for stacked nanosheet device manufacturing[C]// SPIE Advanced Lithography. Proceedings of SPIE. Bellingham: SPIE, 2021, doi: 10.1117/12.2582181.
DOI
|
[16] |
Liu T, Wang D, Pan Z C, et al. Novel post-gate single diffusion break integration in gate-all-around nanosheet transistors to achieve remarkable channel stress for N/P current matching[J]. IEEE Transactions on Electron Devices, 2022, 69(3): 1497-1502.
DOI
URL
|
[17] |
Prasad D, Nibhanupudi S S, Das S, et al. Buried power rails and back-side power grids:ARM CPU power delivery network design beyond 5 nm[C]// IEEE International Electron Devices Meeting (IEDM). Piscataway: IEEE Press, 2020, doi: 10.1109/IEDM19573.2019.8993617.
DOI
|
[18] |
Ryckaert J, Schuddinck P, Weckx P, et al. The complementary FET (CFET) for CMOS scaling beyond N3[C]// IEEE Symposium on VLSI Technology. Piscataway: IEEE Press, 2018, doi: 10.1109/VLSIT.2018.8510618.
DOI
|
[19] |
Milojevic D, Sisto G, Plas G, et al. Fine-pitch 3D system integration and advanced CMOS nodes: Technology and system design perspective[C]// Proceedings of SPIE. Bellingham: SPIE, 2021, doi: 10.1117/12.2584532.
DOI
|
[20] |
半导体行业观察. 一文看懂台积电的技术布局[EB/OL]. [2020-08-26]. http://www.semiinsights.com/s/electronic_comonents/23/40279.shtml.
|