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Future Technical Development Approach for High Computing Power Chips
YAO Peng, SONG Changming, HU Yang, CAI Jian, YIN Shouyi, WU Huaqiang
Abstract1290)   HTML98)    PDF (3065KB)(2522)      

Targeting the future demand for high computing power chips, this paper analyzes the development trends of high computing power chips in China and abroad and further presents an expression of the computing power of a chip involving data interconnection, computing power per transistor, transistor density per unit area, and chip area. It then describes the key technologies for the future development of high computing power chips and explains how these technologies make a difference in accordance with the proposed expression of computing power. Specifically, the current status of these technologies, including advanced integrated circuit manufacturing, monolithic three-dimensional integration, domain-specific architectures, coarse-grained reconfigurable architecture (CGRA), in-memory computing (IMC), chiplets, and wafer-scale integration, in China and abroad and their performance in elevating the computing power of chips are discussed from the perspectives of new materials, new devices, advanced processes, novel architectures, and integrated packaging. The prospects of these technologies and the challenges they face are examined in depth. Regarding the current situation of high computing power chips in China and the restrictions on the development of advanced integrated circuit manufacturing processes, this paper proposes proceeding from the perspective of “architecture + integration + system” to explore an integrated, independently controllable, and innovative approach to high computing power chips. Mature manufacturing processes and novel architectures of CGRA and IMC, together with chiplets based on advanced integration, can be leveraged to achieve breakthroughs in total computing power.

2022, 1 (3): 115-129.   doi: 10.3981/j.issn.2097-0781.2022.03.010